Programmable logic devices (“PLDs”) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (“FPGA”), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (“IOBs”), configurable logic blocks (“CLBs”), dedicated random access memory blocks (“BRAMs”), multipliers, digital signal processing blocks (“DSPs”), processors, clock managers, delay lock loops (“DLLs”), and so forth. Notably, as used herein, “include” and “including” mean including without limitation.
One such FPGA, the Xilinx Virtex® FPGA, is described in detail in pages 3-75 through 3-96 of the Xilinx 2000 Data Book entitled “The Programmable Logic Data Book 2000” (hereinafter referred to as “the Xilinx Data Book”), published April, 2000, available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124. (Xilinx, Inc., owner of the copyright, has no objection to copying these and other pages referenced herein but otherwise reserves all copyright rights whatsoever.) Young et al. further describe the interconnect structure of the Virtex FPGA in U.S. Pat. No. 5,914,616, issued Jun. 22, 1999 and entitled “FPGA Repeatable Interconnect Structure with Hierarchical Interconnect Lines.”
Another such FPGA, the Xilinx Virtex®-II FPGA, is described in detail in pages 33-75 of the “Virtex-II Platform FPGA Handbook”, published December, 2000, available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124. And yet another such FPGA, the Xilinx Virtex-II Pro™ FPGA, is described in detail in pages 19-71 of the “Virtex-II Pro Platform FPGA Handbook”, published Oct. 14, 2002 and available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124.
Another type of PLD is the Complex Programmable Logic Device (“CPLD”). A CPLD includes two or more “function blocks” connected together and to input/output (“I/O”) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (“PLAs”) and Programmable Array Logic (“PAL”) devices. Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, for example, using fuse or antifuse technology.
The terms “PLD” and “programmable logic device” include these exemplary devices, as well as encompassing devices that are only partially programmable. For purposes of clarity, FPGAs are described below though other types of PLDs may be used. FPGAs may include one or more embedded microprocessors. For example, a microprocessor may be located in an area reserved for it, generally referred to as a “processor block.”
A frame of configuration memory for an FPGA, which may be an array of configuration random access memory (“RAM”) cells, conventionally may be loaded with coded configuration information. For example, a frame of configuration information may be stored in an array of configuration RAM cells which is 1312 bits tall by 1 bit wide, where a portion of these cells, such as 12 bits in the center, may be for error correction. Such 12 centrally located bits may be encoded with a known error correction code, such as a Hamming code for example. These 1312 bits may be read out in parallel to a frame data register, which conventionally is a shift register. Shadow registers may be interposed between the frame data register and the configuration memory to facilitate reading out information from the frame of configuration memory while performing a read or write operation using the frame data register. Configuration information may be shifted in or out of the frame data register in 32 bit increments, such as via a 32-bit wide bus. Continuing the above example, 1312 bits read out of a frame data register 32 bits at a time to bit accumulating error correction circuitry would take 41 clock cycles. If an error is detected, an error-corrected bit and all other bits of the frame may be written back into the configuration memory from which they were obtained. This may involve writing all 1312 bits, including the corrected bit, 32 bits at a time to the frame data register, taking another 41 clock cycles. Additionally, there may be some clock cycles for overhead, such as setting up a read of the frame data register, setting up a write of the frame data register, and error calculation. Thus it should be understood that for configuration memory, error checking is a time-consuming process.
Accordingly, it would be desirable and useful to provide means for error correction for configuration memory that takes less time than conventional error correction.